Simulating a LAGS processor to consider variable latency on L1 D-Cache

Resumen

Variability is one of the important issues in deep-submicron tecnologies, and the assumption of non-variable, constant la- tencies in the modules of deep-submicron processors can jeopardize their performance. Cache memories have demon- strated their data-dependent latency due to factors like the coupling capacitances or the distance between the port and the required data. In this paper we present, on one hand, a scheme to detect read operation completion on a variable latency cache mem- ory. On the other hand, we present an asynchronous approach to improve processor performance using this feature. Hence, we propose a Locally-Asynchronous Globally-Synchronous (LAGS) superscalar microarchitecture in which read opera- tions on a variable latency L1 data cache are managed through an asynchronous wrapper. In addition, we demonstrate its fea- sibility running SPEC2000 benchmarks on a 64-bit super- scalar processor modeled through an architectural simulator. Simulations show speedups ranging up to 1.44 and averaging 1.22 over a non-variable cache design.

Publicación
Proceedings of the 2010 Summer Computer Simulation Conference
J. Manuel Colmenar
J. Manuel Colmenar
Artificial Intelligence Professor

Mis intereses de investigación se centran en las metaheurísticas aplicadas a problemas de optimización. He trabajado en diferentes problemas de optimización combinatoria aplicando algoritmos trajectoriales como GRASP o VNS. Además, estoy muy interesado en las aplicaciones de la Evolución Gramatical, específicamente en el dominio de los modelos y la predicción, como alternativa a los enfoques de aprendizaje automático.