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A power-aware technique for functional units in high-performance processors
This paper presents a hardware technique to reduce the static and dynamic power consumption in functional units of a 64-bit superscalar …
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A technique to reduce static and dynamic power of functional units in high-performance processors
This paper presents a hardware technique to reduce both the static and dynamic power consumption in Functional Units of a 64-bit …
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Comparing the performance of a 64-bit fully-asynchronous superscalar processor versus its synchronous counterpart
Nowadays, synchronous processor designers have to deal with severe problems related to the distribution of a complex clock network like …
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Experiencia en el desarrollo y utilización de una herramienta de corrección automática de exámenes
En este trabajo se presentan dos partes bien diferenciadas. Por un lado, la experiencia vivida en el proceso de desarrollo y mejora de …
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Sim-async: An architectural simulator for asynchronous processor modeling using distribution functions
In this paper we present sim-async, an architectural simulator able to model a 64-bit asynchronous superscalar microarchitecture. The …
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Testing in math course a new tool for online exams automatically graded: a teaching and learning experience
In this paper we analyze the usage of ExaNet: an online exam and evaluation management tool. To do so, we proceeded to use this tool to …
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Adaptación de un simulador de potencia para unidades funcionales en procesadores de alto rendimiento
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Experiencia educativa entre varias asignaturas
Se presenta la experiencia educativa desarrollada entre varias asignaturas para la construcción de una herramienta de …
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Power reduction of superscalar processor functional units by resizing adder-width
This paper presents a hardware technique to reduce of static and dynamic power consumption in FUs. This approach entails substituting …
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Empirical characterization of the latency of long asynchronous pipelines with data-dependent module delays
The paper has two aims: on one hand, to characterize the nature of the relationship between the latency of an asynchronous pipeline and …
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