Sonia López

Recientes

• Reducing power of functional units in high-performance processors by checking instruction codes and resizing adders (2007)
• Sim-async: An architectural simulator for asynchronous processor modeling using distribution functions (2006)
• A technique to reduce static and dynamic power of functional units in high-performance processors (2006)
• Enhancing GALS processor performance using data classification based on data latency (2004)
• Empirical characterization of the latency of long asynchronous pipelines with data-dependent module delays (2004)