Blog
Eventos
Investigadores
Proyectos
Publicaciones
Líneas de investigación
Heuristicas.es
Optsicom
Contacto
Español
English
Sonia López
Recientes
Reducing power of functional units in high-performance processors by checking instruction codes and resizing adders
A technique to reduce static and dynamic power of functional units in high-performance processors
Sim-async: An architectural simulator for asynchronous processor modeling using distribution functions
Empirical characterization of the latency of long asynchronous pipelines with data-dependent module delays
Enhancing GALS processor performance using data classification based on data latency
Citar
×