Oscar Garnica

Recientes

Obtaining Difference Equations for~Glucose Prediction by~Structured Grammatical Evolution and~Sparse Identification
Blood glucose prediction using multi-objective grammatical evolution: analysis of the “agnostic” and “what-if” scenarios
Short and Medium Term Blood Glucose Prediction Using Multi-objective Grammatical Evolution
Determination of microscopic residual stresses using diffraction methods, EBSD maps, and evolutionary algorithms
Structured grammatical evolution for glucose prediction in diabetic patients
Identification of models for glucose blood values in diabetics by grammatical evolution
Data based prediction of blood glucose concentrations using evolutionary methods
Enhancing grammatical evolution through data augmentation: application to blood glucose forecasting
Compilable phenotypes: speeding-up the evaluation of glucose models in grammatical evolution
Optimizing L1 cache for embedded systems through grammatical evolution
Data-based identification of prediction models for glucose
Optimizing Performance of L1 Cache Memory for Embedded Systems driven by Differential Evolution
Clarke and parkes error grid analysis of diabetic glucose models obtained with evolutionary computation
Real time evolvable hardware for optimal reconfiguration of cusp-like pulse shapers
Solving ga-hard problems with EMMRS and GPGPUs
Quantifying the impact of dynamic memory managers into memory-intensive applications
A parallel evolutionary algorithm to optimize dynamic memory managers in embedded systems
Improving reliability of embedded systems through dynamic memory manager optimization using grammatical evolution
Simulating a LAGS processor to consider variable latency on L1 D-Cache
Characterizing asynchronous variable latencies through probability distribution functions
T1 Advanced Architectures
Reducing power of functional units in high-performance processors by checking instruction codes and resizing adders
A power-aware technique for functional units in high-performance processors
A technique to reduce static and dynamic power of functional units in high-performance processors
Sim-async: An architectural simulator for asynchronous processor modeling using distribution functions
Métricas, metodologías y herramientas de simulación para evaluar mejoras en arquitecturas de bajo consumo
Power reduction of superscalar processor functional units by resizing adder-width
Empirical characterization of the latency of long asynchronous pipelines with data-dependent module delays
Enhancing GALS processor performance using data classification based on data latency