Oscar Garnica

Recientes

• Obtaining Difference Equations for~Glucose Prediction by~Structured Grammatical Evolution and~Sparse Identification (2022)
• Blood glucose prediction using multi-objective grammatical evolution: analysis of the “agnostic” and “what-if” scenarios (2021)
• Short and Medium Term Blood Glucose Prediction Using Multi-objective Grammatical Evolution (2020)
• Structured grammatical evolution for glucose prediction in diabetic patients (2019)
• Determination of microscopic residual stresses using diffraction methods, EBSD maps, and evolutionary algorithms (2019)
• Identification of models for glucose blood values in diabetics by grammatical evolution (2018)
• Enhancing grammatical evolution through data augmentation: application to blood glucose forecasting (2017)
• Data based prediction of blood glucose concentrations using evolutionary methods (2017)
• Optimizing L1 cache for embedded systems through grammatical evolution (2016)
• Compilable phenotypes: speeding-up the evaluation of glucose models in grammatical evolution (2016)
• Optimizing Performance of L1 Cache Memory for Embedded Systems driven by Differential Evolution (2015)
• Data-based identification of prediction models for glucose (2015)
• Solving ga-hard problems with EMMRS and GPGPUs (2014)
• Real time evolvable hardware for optimal reconfiguration of cusp-like pulse shapers (2014)
• Clarke and parkes error grid analysis of diabetic glucose models obtained with evolutionary computation (2014)
• Quantifying the impact of dynamic memory managers into memory-intensive applications (2011)
• Simulating a LAGS processor to consider variable latency on L1 D-Cache (2010)
• Improving reliability of embedded systems through dynamic memory manager optimization using grammatical evolution (2010)
• A parallel evolutionary algorithm to optimize dynamic memory managers in embedded systems (2010)
• Characterizing asynchronous variable latencies through probability distribution functions (2009)
• T1 Advanced Architectures (2008)
• Reducing power of functional units in high-performance processors by checking instruction codes and resizing adders (2007)
• Sim-async: An architectural simulator for asynchronous processor modeling using distribution functions (2006)
• A technique to reduce static and dynamic power of functional units in high-performance processors (2006)
• A power-aware technique for functional units in high-performance processors (2006)
• Power reduction of superscalar processor functional units by resizing adder-width (2005)
• Métricas, metodologías y herramientas de simulación para evaluar mejoras en arquitecturas de bajo consumo (2005)
• Enhancing GALS processor performance using data classification based on data latency (2004)
• Empirical characterization of the latency of long asynchronous pipelines with data-dependent module delays (2004)