Guadalupe Miñana

Recientes

• Reducing power of functional units in high-performance processors by checking instruction codes and resizing adders (2007)
• Sim-async: An architectural simulator for asynchronous processor modeling using distribution functions (2006)
• A technique to reduce static and dynamic power of functional units in high-performance processors (2006)
• A power-aware technique for functional units in high-performance processors (2006)
• Power reduction of superscalar processor functional units by resizing adder-width (2005)
• Métricas, metodologías y herramientas de simulación para evaluar mejoras en arquitecturas de bajo consumo (2005)