Enhancing GALS processor performance using data classification based on data latency


This paper proposes a new approach for improving the performance of Globally Asynchronous Locally Synchronous (GALS) circuits. This approach takes advantage of the delay dependence of the input vectors to classify input data into several classes. Each class has a clock period associated, in such a way that a suitable clock is selected for each data. This technique has been applied to a GALS pipelined RISC processor based on DLX processor. Several programs were run over this processor performing different classifications, in order to check the viability of this new approach.

International Workshop on Power and Timing Modeling, Optimization and Simulation
J. Manuel Colmenar
J. Manuel Colmenar
Associate Professor

My research interests are focused on metaheuristics applied to optimization problems. I have worked on different combinatorial optimization problems applying trajectorial algorithms such us GRASP or VNS. Besides, I am very interested in applications of Grammatical Evolution, specifically in model and prediction domain, as alternative to machine learning approaches.