Simulating a LAGS processor to consider variable latency on L1 D-Cache

Abstract

Variability is one of the important issues in deep-submicron tecnologies, and the assumption of non-variable, constant la- tencies in the modules of deep-submicron processors can jeopardize their performance. Cache memories have demon- strated their data-dependent latency due to factors like the coupling capacitances or the distance between the port and the required data. In this paper we present, on one hand, a scheme to detect read operation completion on a variable latency cache mem- ory. On the other hand, we present an asynchronous approach to improve processor performance using this feature. Hence, we propose a Locally-Asynchronous Globally-Synchronous (LAGS) superscalar microarchitecture in which read opera- tions on a variable latency L1 data cache are managed through an asynchronous wrapper. In addition, we demonstrate its fea- sibility running SPEC2000 benchmarks on a 64-bit super- scalar processor modeled through an architectural simulator. Simulations show speedups ranging up to 1.44 and averaging 1.22 over a non-variable cache design.

J. Manuel Colmenar

Full Professor

My research interests are focused on metaheuristics applied to optimization problems. I have worked on different combinatorial optimization problems applying trajectorial algorithms such us GRASP or VNS. Besides, I am very interested in applications of Grammatical Evolution, specifically in model and prediction domain, as alternative to machine learning approaches.