Asynchronous systems are attracting the interest of a growing number of designers. However, the lack of simulation tools devoted to asynchronous microarchitectures is a gap that is not narrowed today. One of the main obstacles on the simulation of asynchronous systems is the variable computation delays of their modules, which compute as fast as possible under the actual conditions of the system because there is no clock signal. In this paper we present a modelling method that describes the variable computation delay of an asynchronous circuit by using probability distribution functions that return the probability of a given delay to be spent on the computation of a data. This method was integrated in an architectural simulator of a 64-bit superscalar asynchronous microarchitecture where the computation delay of each one of the modules of the microarchitecture was characterized through a probability distribution function. The experimental results showed that the asynchronous behavior was successfully modeled, and the architectural simulations of standard benchmarks were affordable in terms of wall-clock simulation time.