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Comparing the performance of a 64-bit fully-asynchronous superscalar processor versus its synchronous counterpart
Nowadays, synchronous processor designers have to deal with severe problems related to the distribution of a complex clock network like …
S. Lopez
,
G. Minana
,
J. I. Hidalgo
,
J. Lanchares
,
O. Garnica
,
C. E. S. Felipe
,
J. Manuel Colmenar
Cite
DOI
Experiencia en el desarrollo y utilización de una herramienta de corrección automática de exámenes
En este trabajo se presentan dos partes bien diferenciadas. Por un lado, la experiencia vivida en el proceso de desarrollo y mejora de …
Nuria Joglar
,
José Luis Risco
,
Rubén Sánchez
,
J. Manuel Colmenar
,
Alberto Díaz
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Sim-async: An architectural simulator for asynchronous processor modeling using distribution functions
In this paper we present sim-async, an architectural simulator able to model a 64-bit asynchronous superscalar microarchitecture. The …
J. Manuel Colmenar
,
Oscar Garnica
,
Juan Lanchares
,
José Ignacio Hidalgo
,
Guadalupe Miñana
,
Sonia López
Cite
DOI
Testing in math course a new tool for online exams automatically graded: a teaching and learning experience
In this paper we analyze the usage of ExaNet: an online exam and evaluation management tool. To do so, we proceeded to use this tool to …
Nuria Joglar Prieto
,
José Luis Risco Martín
,
Rubén Sánchez
,
J. Manuel Colmenar
,
Alberto Díaz
Cite
Adaptación de un simulador de potencia para unidades funcionales en procesadores de alto rendimiento
María Guadalupe Miñana Ropero
,
Antonio Óscar Garnica Alcazar
,
José Ignacio Hidalgo
,
Juan Lanchares Dávila
,
J. Manuel Colmenar
Cite
Experiencia educativa entre varias asignaturas
Se presenta la experiencia educativa desarrollada entre varias asignaturas para la construcción de una herramienta de …
Alberto Díaz
,
J. Manuel Colmenar
,
José Luis Risco
,
Nuria Joglar
,
Rubén Sánchez
,
Diego J. Bodas
,
Francisco José Soltero
,
others
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Power reduction of superscalar processor functional units by resizing adder-width
This paper presents a hardware technique to reduce of static and dynamic power consumption in FUs. This approach entails substituting …
Guadalupe Miñana
,
Oscar Garnica
,
José Ignacio Hidalgo
,
Juan Lanchares
,
J. Manuel Colmenar
Cite
DOI
Empirical characterization of the latency of long asynchronous pipelines with data-dependent module delays
The paper has two aims: on one hand, to characterize the nature of the relationship between the latency of an asynchronous pipeline and …
J. Manuel Colmenar
,
Oscar Garnica
,
Sonia López
,
José Ignacio Hidalgo
,
Juan Lanchares
,
Román Hermida
Cite
DOI
Enhancing GALS processor performance using data classification based on data latency
This paper proposes a new approach for improving the performance of Globally Asynchronous Locally Synchronous (GALS) circuits. This …
Sonia López
,
Oscar Garnica
,
J. Manuel Colmenar
Cite
DOI
Hybrid heuristic and mathematical programming in oil pipelines networks
We solve the problem of the distribution of petroleum products through oil pipelines networks. This problem is modeled and solved using …
J. M. de la Cruz
,
J. L. Risco
,
Alberto Herrán González
,
P. Fernández
Cite
DOI
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