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Guadalupe Miñana

Reducing power of functional units in high-performance processors by checking instruction codes and resizing adders
A power-aware technique for functional units in high-performance processors
A technique to reduce static and dynamic power of functional units in high-performance processors
Sim-async: An architectural simulator for asynchronous processor modeling using distribution functions
Métricas, metodologías y herramientas de simulación para evaluar mejoras en arquitecturas de bajo consumo
Power reduction of superscalar processor functional units by resizing adder-width

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